1樓：
module barrel_org(s,a_p,b_p);
input [2:0] s;
input [7:0] a_p;
input [7:] b_p;
reg [7:0] b_p;
always@(a_p or s)
begin
case(s)
3'b000:
begin
b_p <= a_p;
end3'b001:
begin
b_p[7] <= a_p[0];
b_p[6:0] <= a_p[7:1];
end3'b010:
begin
b_p[7:6] <= a_p[1:0];
b_p[5:0] <= a_p[7:2];
end3'b011:
begin
b_p[7:5] <= a_p[2:0];
b_p[4:0] <= a_p[7:3];
end3'b100:
begin
b_p[7:4] <= a_p[3:0];
b_p[3:0] <= a_p[7:4];
end3'b101:
begin
b_p[7:3] <= a_p[4:0];
b_p[2:0] <= a_p[7:5];
end3'b110:
begin
b_p[7:2] <= a_p[5:0];
b_p[1:0] <= a_p[7:6];
end3'b111:
begin
b_p[7:1] <= a_p[6:0];
b_p[0] <= a_p[7];
enddefault:
begin
b_p = a_p;
endendcase
endendmodule
2樓：匿名使用者
always @(posedge clk)begin
data<=;//迴圈左移
//data<=;//迴圈右移end
用verilog hdl程式設計設計8位左右移移位暫存器電路。
3樓：匿名使用者
module verilog1(clk,ldn,k,d,q);
input clk,ldn,k;
input [7:0] d;
output [7:0] q;
reg[7:0] d_reg,q_reg;
always@(negedge ldn)
if(!ldn)
d_reg <= d;
always@(posedge clk )begin
if(k)
begin//right
q_reg[7:0] <= ;
endelse q_reg[7:0] <= ;
endassign q = q_reg;
endmodule
用vfp中的for迴圈語句寫階乘
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求1 2 3n 的和,用C語言巢狀迴圈格式寫
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